Project Description:

Time to Digital Converter (TDC) is a widely used high-precision time interval measurement unit. The TDC is known to suffer from the nonliearity problem and is vulnerable to temperature variations. To tackle this issue, conventional approaches often entail excessive redundant resources or cumbersome calibrations, or alternatively sacrifice conversion rates. In light of this, in this paper, we propose ParCha, a new resource-efficient and calibration-free TDC using Parallel short Chains. ParCha is a variant of low dead time Tapped Delay Line (TDL) TDC but we ``fold'' the long delay chain into several short parallel pieces. The key insight here is to reallocate the measurement range of each short piece by introducing appropriate fix delay, so that they can equivalently formulate a long chain. This can effectively minimize delay cell heterogeneity, thereby eliminating the reliance on tedious calibrations. Additionally, our design utilizes less temperature-sensitive resources but relies more on temperature-invariant modules so that our design can be more resilient to temperature fluctuations. We have implemented our TDC structure in popular FPGA platforms. Results demonstrate that our TDC can readily achieve a less than 0.3~\! LSB INL even without any calibration tricks.

Acknowledgement:

• This project is filed on December 2021 and is patented. For more information please visit our git repository

  People:

  • Dr. Chao Cai (Associate Proffessor, College of Life Science & Engineering) - Huazhong University of Science and Technology
  • Fei Wang(Ph.D student, College of Life Science & Engineering) - HUST
  • Jiawen Zhou (Master student, College of Life Science & Engineering) - HUST
  • Ziyi Wong (Master student, College of Life Science & Engineering) - HUST

  Related Publications:

• [1] Chao Cai. "ParCha: A New Resource-efficient and Calibration-free TDC using Parallel Short Chains", in arxiv,2023